1. Field of the Invention
The present invention relates generally to programmable logic devices, and more particularly to programmable logic devices configured for wireless communication.
2. Description of the Related Art
Programmable logic devices exist as a well-known type of integrated circuit (IC) that may be programmed by a user to perform specified logic functions. There are different types of programmable logic devices, such as programmable logic arrays (PLAs) and complex programmable logic devices (CPLDs). One type of programmable logic devices, called a field programmable gate array (FPGA), is very popular because of a superior combination of capacity, flexibility and cost. An FPGA typically includes an array of configurable logic blocks (CLBs) surrounded by a ring of programmable input/output blocks (IOBs). The CLBs and IOBs are interconnected by a programmable interconnect structure. The CLBs, IOBs, and interconnect structure are typically programmed by loading a stream of configuration data (bitstream) into internal configuration memory cells that define how the CLBs, IOBs, and interconnect structure are configured. The configuration bitstream may be read from an external memory, conventionally an external integrated circuit memory EEPROM, EPROM, PROM, and the like, though other types of memory may be used. The collective states of the individual memory cells then determine the function of the FPGA.
Even though FPGAs are very flexible and can be used to implement many circuits, they have some performance limitations, such as longer signal delays and lower gate counts. These limitations hinder use of FPGAs on high-speed communication applications, namely, those communication applications with real-time processing of information. For these applications, application specific integrated circuits (ASICs) are generally used.
Unfortunately, communication circuits implemented as ASICs have several disadvantages. One such disadvantage is the time-to-market risks associated with the relatively long cycle time necessary for the implementation of a new ASIC design. An additional disadvantage of using ASICs for communication circuits is that ASICs are “hardwired” and thus conventionally are not reconfigurable for a new application or application upgrade.
Wireless Local Area Network (WLAN) radio technology comprising IEEE 802.11a and HiperLAN2 are two forms of next generation communication. The physical layer of both IEEE 802.11a and HiperLAN2 technologies is the same, namely, Orthogonal Frequency Division Multiplex (OFDM). However, the data link layer of each of these technologies is different. The data link layer comprises the medium access control (MAC) and logical link control layers. The physical layer defines electrical, mechanical and procedural specifications, which provide transmission of bits over a communication medium or channel. WLAN physical layer technologies include narrowband radio, spread spectrum and, with reference to the above-identified LAN technologies, OFDM. The logical link layer ensures error control and synchronization between physically connected devices communicating over a channel, and ensures priority determinations and allocations for access to such channel.
Both IEEE 802.11a and HiperLAN2 use a 5 GHz ISM (Industrial, Scientific, Medical) band. However, unknown future unification to a single standard, namely, either IEEE 802.11a or HiperLAN2, is causing concern among those deciding on which version of OFDM to implement in their products. In addition, nonconformance to a single standard is hampering benefits associated with economies of scale.
Accordingly, it would be desirable and advantageous to have available a programmable logic device which is capable of implementing either IEEE 802.11a or HiperLAN2.